An imaging sensor is a device that is capable of sensing imagery based on light focused thereon. A machine visual sensing system or a vision sensor may be defined as an imaging sensory system having both image sensing and image processing functions, whether these functions are all performed primarily on a single chip or on a multiple chip system. In a “neuromorphic” approach, some or all computations may be performed with analog or mixed-signal circuits (i.e. mixed analog and digital) which exploit the physical dynamics inherent in VLSI (very large scale integration) circuitry and may additionally mimic biological structures. One source that provides such “neuromorphic” approaches is a book entitled “Analog VLSI and Neural Systems” by C. Mead, published by Addison Wesley in 1989. A related approach is to use “vision chips”, which are defined herein to be integrated circuits having both image acquisition circuitry and image processing circuitry in the same device, including within the same monolithic die or integrated circuit. One book that provides methods of implementing vision chips is “Vision Chips” by A. Moini and published by Kluwer Academic Publishing in 1999. When either of the above mentioned approaches is properly executed, it is possible to implement a machine vision system capable of performing a given set of tasks in a package substantially smaller than that when utilizing a conventional CMOS (complementary metal-oxide-semiconductor) or CCD (charge coupled device) imager connected to a high-performance processor. Many image processing tasks involve the detection of visual features, such as edges.
Refer to FIG. 1, which illustrates a prior art focal plane array 101 of active pixel circuits, as would be fabricated in a P-substrate/N-well semiconductor process. For purposes of discussion, all circuits in this document will be described for P-substrate/N-well processes. These circuits may be converted for other semiconductor processes. This focal plane array 101 may be fabricated on an imaging chip located at the focal plane of an optical apparatus or a lens, and thus configured to obtain an image from the visual field. The depicted focal plane array 101 has a two-by-two array of active pixel circuits. A two-by-two array is shown in FIG. 1 for purposes of illustration, however a larger array size may be fabricated by adding rows and columns of active pixel circuits. Active pixel circuit 103 comprises a photodiode 111, a sampling capacitor 113, a resetting transistor 115, a sampling transistor 117, a buffering transistor 119, and a selecting transistor 121. The gate of resetting transistor 115 is connected to a global signal nreset 131. The gate of sampling transistor 117 is connected to a global signal samp 133. Signals nreset 131 and samp 133 are global and thus connected to all active pixel circuits in the array 101. The other active pixel circuits are similarly constructed.
Note three symbols used to indicate three types of nodes in the schematic diagram of FIG. 1. Double rectangles, for example that associated with node samp 133, indicate that the node is a global node. All instances of a global node having the same name are electrically connected together. The five-sided symbol connecting to a wire via a point, for example node rowsel1 141, indicates an input port to a circuit. The five-sided symbol connecting to a wire via a flat side, for example the symbol labeled column1 at node 143, indicates an output port from the circuit. Global nodes, input ports, and output ports will be similarly denoted throughout this document.
Photodiode 111 may be formed from a PN junction between the P-substrate, which is tied to Ground 102, and N-doped silicon such as N-diffusion or an N-well. When light strikes photodiode 111, the photodiode 111 sinks current from node 123 to Ground 102 at a rate proportional to the amount of light striking the photodiode 111.
The circuit 101 is operated as follows: First the active pixel circuits are reset by setting global signals nreset 131 and samp 133 to a digital low. This turns on resetting transistor 115 and sampling transistor 117. Node 123 and node 125 become connected together and are set to a potential equal to the power supply voltage Vdd 104. Node 125 is referred to herein as the “sampling node”. Setting the sampling node 125 to Vdd 104 discharges the sampling capacitor 113.
Second, signal nreset 131 is set to a digital high. This turns off resetting transistor 115. Nodes 123 and 125 are still connected together via sampling transistor 117 and so will have the same potential.
Third, the active pixel circuits are allowed to integrate. As light strikes photodiode 111, current is sunk from node 123 to Ground. This current charges capacitor 113. Since node 123 and node 125 are connected together via sampling transistor 117, they will together fall in potential as the photodiode 111 sinks current to Ground 102 and as sampling capacitor 113 charges. The more intense the light striking the photodiode 111 is, the faster capacitor 113 will charge and the faster the potential at nodes 123 and 125 will fall. The active pixel circuits will next integrate over a time period called the integration interval.
Fourth, after delaying by the integration interval, the signal samp 133 is set to a digital high. This turns off sampling transistor 117 which disconnects node 123 from node 125 and thus stops the integration of the photodiode's current on sampling capacitor 113. The potential at node 125 will then remain a constant value due to capacitor 113 (except for minute changes due to any leakage currents). The potential at node 125 will contain a reading of the amount of light striking photodiode 111, with a lower potential corresponding to a higher light intensity.
Fifth, the potential at node 125 may be read out by turning on row select line rowsel1 141. This turns on selecting transistor 121, which causes buffering transistor 119 and transistor 151 to form a source follower circuit. Global bias voltage nbias 135 is set to a voltage sufficiently positive to allow the source follower circuit to operate. The resulting signal, called a photoreceptor signal, may be read out at node 143 without significantly affecting the voltage at node 125.
The entire focal plane array 101 may be operated simultaneously, and then individual rows may be read out sequentially. For example, the first through fourth steps above may be performed. Then, in the fifth step when row select line rowsel1 141 is set to a digital high, pixel circuit 103 is read out at output node 143 and pixel circuit 105 is read out at output node 145. Nodes 143 and 145 may also be referred to as column readout lines. The potentials at nodes 143 and 145, when rowsel1 141 is digital high, may be referred to as photoreceptor signals generated by pixel circuits 103 and 105. Then, row select line rowsel1 141 is set to a digital low, and row select line rowsel2 142 is set to a digital high. This allows the other two active pixel circuits to be read out. The act of performing the above steps and reading out the photoreceptor signals over the entire array 101 may be referred to as the act of grabbing an image, including if these photoreceptor signals are recorded or digitized or processed by other circuitry or devices (not shown). The collection of photoreceptor signals generated by all rows of pixel circuits may be referred to as an image.
Care must be taken to select an integration interval for a particular environment. If the integration interval is too long, then active pixel circuits imaging brighter areas of the visual field will saturate since the sampling nodes (e.g. node 125 for pixel circuit 103) cannot drop below a potential based on Ground 102. If the integration interval is too short, then the sampling capacitors in the active pixel circuits imaging darker areas of the visual field will accumulate very small charge, resulting in a poor quality measurement. Typical methods for selecting an integration interval involve grabbing an image with an initial integration interval, and then increasing the integration interval if the grabbed image is too dark or decreasing the integration interval if pixels are saturated.
The prior art focal plane circuit 101 has a significant disadvantage: The dynamic range of light levels that can be concurrently imaged is limited by the fact that the charge across the sampling capacitors (e.g. capacitor 113) is a linear function of light intensity. If some regions of the visual field are very bright while other regions are dim, then the integration interval may be set to optimally image either the brighter areas or the darker areas but not both. This weakness limits the usefulness of the focal plane circuit 101 in many real-world environments that have wide range of light levels.
A second disadvantage of the focal plane circuit 101 is that the photoreceptor signals are analog values and need to be digitized before they can be processed by a processor. It is desirable to have circuits that may perform elementary image processing functions directly in circuitry, so that these functions do not need to be performed on a processor.